1. Field of the Invention
The present invention relates to a semiconductor memory device having a spare memory cell.
2. Description of the Background Art
The arrangement of a main portion of a conventional semiconductor memory device will be described in relation to FIG. 10. In the diagram, memory cells are represented by reference characters m0 to m63, word lines disposed corresponding to the rows are represented by reference characters w0 to w63, and a bit line disposed corresponding to a column is represented by reference characters xe2x80x9cbit,xe2x80x9d respectively. Further, a spare memory cell that can replace a memory cell is represented by reference characters r0, and a spare word line that can replace a word line is represented by reference characters sw0.
Bit line xe2x80x9cbitxe2x80x9d is connected to memory cells m0 to m63 and spare memory cell r0, and transmits data read from or to be written into memory cells m0 to m63 and spare memory cell r0. Word lines w0 to w63 are connected to memory cells m0 to m63, and each word line sends a selecting signal to a corresponding memory cell. Spare word line sw0 is connected to spare memory cell r0 and sends a selecting signal to the corresponding spare memory cell.
As shown in FIG. 10, the conventional semiconductor memory device includes a replacement control circuit 100#0, a decoder 105#0 including programming circuits 102#0 to 102#5 and logic circuits 103#0 to 103#63, a comparator 120#0, and an AND circuit 119#0. Each of replacement control circuit 100#0 and programming circuits 102#0 to 102#5 includes a fuse.
When a defective memory cell is replaced with a spare memory cell (using spare word line sw0), the fuse included in replacement control circuit 100#0 is blown. Thus, a replacement control signal R0 of a logic high or H level indicating the use of the spare memory cell will be output.
The fuse included in each of programming circuits 102#0 to 102#5 is blown according to an address of the defective memory cell. The output from the programming circuit having a blown fuse attains the H level. Signals g0 to g5 are output from programming circuits 102#0 to 102#5.
Comparator 120#0 compares a 6-bit address signal ad less than 0:5 greater than  with signals g0 to g5, and outputs an H level signal when a match occurs. AND circuit 119#0 activates spare word line sw0 according to replacement control signal R0 and a comparison result from comparator 120#0.
Logic circuits 103#0 to 103#63 each include AND circuits 104A and 104B and an NAND circuit 106. Logic circuits 103#0 to 103#63 are provided corresponding to a 64-bit address. Each of logic circuits 103#0 to 103#63 receives a signal g0 or an inverted signal /g0 of signal g0, a signal g1 or an inverted signal /g1 of signal g1, a signal g2 or an inverted signal /g2 of signal g2, a signal g3 or an inverted signal /g3 of signal g3, a signal g4 or an inverted signal /g4 of signal g4, and a signal g5 or an inverted signal /g5 of signal g5.
In the diagram, logic circuit 103#0 receives signals g0, g1, g2, g3, g4, and g5, while logic circuit 103#63 receives signals /g0, /g1, /g2, /g3, /g4, and /g5. NAND circuit 106 receives replacement control signal R0 and outputs from AND circuits 104A and 104B. Row address non-selection signal t0 to t63 are output from logic circuits 103#0 to 103#63, respectively.
The conventional semiconductor memory device further includes AND circuits 108#0 to 108#63. AND circuits 108#0 to 108#63 are respectively provided to word lines w0 to w63. AND circuits 108#0 to 108#63 receive row address nonselection signals t0 to t63 and decode signals a0 to a63, respectively. Decode signals a0 to a63 are obtained by decoding address signal ad less than 0:5 greater than  by a row decoder not shown. Word lines w0 to w63 are respectively activated according to outputs from AND circuits 108#0 to 108#63.
When the memory cells are all normal, replacement control signal R0 is at a logic low or L level so that spare word line sw0 is in the inactive state. In this case, row address non-selection signals t0 to t63 attain the H level. One of word lines w0 to w63 is activated according to decode signals a0 to a63.
When a defect is found in a memory cell and the defective memory cell is to be replaced with a spare memory cell, a fuse in replacement control circuit 100#0 and a corresponding fuse in programming circuits 102#0 to 102#5 are blown.
An example is given in which a memory cell m0 is defective. Assume that the address of word line w0 is xe2x80x9c000000xe2x80x9d (=ad less than 0:5 greater than ). In this case, all the fuses in programming circuits 102#0 to 102#5 are blown. Signals g0 to g5 all attain the H level so that signal t0 output from logic circuit 103#0 attains the L level. Consequently, when an address signal designating memory cell m0 is input and decode signal a0 attains the H level, word line w0 is not activated.
At this time, comparator 120#0 outputs an H level signal since the input address signal ad less than 0:5 greater than  corresponds to signals g0 to g5. As a result, spare word line sw0 is activated.
FIG. 11 shows another arrangement of the main portion of a conventional semiconductor memory device. The conventional semiconductor memory device shown in FIG. 11 has an arrangement for replacing two word lines. In the diagram, spare memory cells that can replace the memory cells are represented by reference characters r0 and r1, and spare word lines that can replace word lines are represented by reference characters sw0 and sw1.
A bit line xe2x80x9cbitxe2x80x9d is connected to memory cells m0 to m63 and spare memory cells r0 and r1, and transmits data read from or to be written into memory cells m0 to m63 and spare memory cells r0 and r1. Spare word lines sw0 and sw1 are connected to spare memory cells r0 and r1, and each spare word line sends a selecting signal to a corresponding spare memory cell.
As shown in FIG. 11, the conventional semiconductor memory device includes replacement control circuits 100#0 and 100#1, decoders 105#0 and 105#1, comparators 120#0 and 120#1, and AND circuits 119#0 and 119#1.
Replacement control circuit 100#1 has the same arrangement as replacement control circuit 100#0, and its fuse is blown when spare word line sw1 is to be used. Consequently, an H level replacement control signal R1 is output.
The arrangement of decoder 105#1 is the same as that of decoder 105#0. The fuse included in each of programming circuits 102#0 to 102#5 is blown according to an address of a defective memory cell. Hereinafter, the outputs from programming circuits 102#0 to 102#5 included in decoder 105#1 will be referred to as signals h0 to h5.
Each of logic circuits 103#0 to 103#63 included in decoder 105#1 receives a signal h0 or an inverted signal /h0 of signal h0, a signal h1 or an inverted signal /h1 of signal h1, a signal h2 or an inverted signal /h2 of signal h2, a signal h3 or an inverted signal /h3 of signal h3, a signal h4 or an inverted signal /h4 of signal h4, and a signal h5 or an inverted signal /h5 of signal h5. Logic circuits 103#0 to 103#63 perform logical processing according to replacement control signal R1. Row address non-selection signals output from decoder 105#1 will be referred to as signals u0 to u63.
Comparator 120#1 has the same arrangement as comparator 120#0, compares address signal ad less than 0:5 greater than  with signals h0 to h5, and outputs an H level signal when a match occurs. AND circuit 119#1 activates spare word line sw1 according to replacement control signal R1 and a comparison result from comparator 120#1.
The conventional semiconductor memory device shown in FIG. 11 further includes AND circuits 110#0 to 110#63 and 108#0 to 108#63. AND circuits 110#0 to 110#63 and AND circuits 108#0 to 108#63 are respectively provided to word lines w0 to w63.
An AND circuit 110#i (i=0, 1, . . . , 63) receives row address non-selection signals ti and ui. AND circuit 108#i receives a decode signal ai and an output from AND circuit 110#i.
When the row address non-selection signal output from decoder 105#0 or the row address non-selection signal output from decoder 105#1 is at the L level, the corresponding word line remains inactivate regardless of the input address signal.
When all memory cells are normal, replacement control signals R0 and R1 attain the L level so that spare word lines sw0 and sw1 are in the inactive state. On the other hand, row address non-selection signals are all at the H level so that one of word lines w0 to w63 is activated according to decode signals a0 to a63.
For instance, when defects are found in memory cells m0 and m1, fuses in replacement control circuits 100#0 and 100#1, fuses in programming circuits 102#0 to 102#5 included in decoder 105#0, and fuses in programming circuits 102#0 to 102#4 included in decoder 105#1 are blown.
As a result, replacement control signals R0 and R1 attain the H level. At this time, row address non-selection signal t0 and signal u1 attain the L level. Consequently, outputs from AND circuits 110#0 and 110#1 attain the L level, and outputs from AND circuits 110#2 to 110#63 attain the H level.
Word line w0 or word line w1 is not activated even when an address signal designating the defective memory cell m0 or the defective memory cell m1 is input (even when decode signal a0 or a1 is at the H level).
On the other hand, when the input address signal ad less than 0:5 greater than  corresponds to signals g0 to g5 in comparator 120#0, spare word line sw0 is activated. When the input address signal ad less than 0:5 greater than  corresponds to signals h0 to h5 in comparator 120#1, spare word line sw1 is activated.
Thus configured, the conventional semiconductor memory device can perform normal processing using a spare word line instead of the word line connected to a defective memory cell.
Being configured in the above-described manner, however, the conventional semiconductor memory device requires fuses (of the number that equals the number of addresses) necessary for programming the defective addresses as well as fuses for controlling the use of a spare memory cell (replacement control circuit).
Consequently, in order to replace the defective memory cells that exist over a plurality of rows by using a plurality of spare word lines, fuses of the number derived from first adding one to the number of addresses and then multiplying the sum by the number of spare word lines would be required.
As a result, when the number of spare word lines is increased for repairing defective memory cells, the region for mounting the fuses also increases, which interferes with the reduction in the overall chip area.
Thus, the present invention provides a semiconductor memory device capable of replacing a defective memory cell with a spare memory cell with small area requirement.
The semiconductor memory device according to the present invention is provided with a normal memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, and a plurality of memory lines for storing data into or reading stored data from the plurality of memory cells; a spare memory cell array including a plurality of spare memory cells and a plurality of spare memory lines, each provided for replacing a defective memory line of the plurality of memory lines, for storing data into or reading stored data from a corresponding spare memory cell; and a replacement programming portion including a plurality of programming portions, each of the plurality of programming portions having a prescribed number of fuses required for programming an address of the defective memory line; and semiconductor memory device further provided with a select control circuit for performing a replacement according to a programmed state of the plurality of programming portions.
Preferably, the replacement programming portion includes a plurality of logic circuits respectively provided to the plurality of programming portions, each of the plurality of logic circuits outputs a selecting signal of a prescribed level when at least one fuse out of the prescribed number of fuses is blown. The select control circuit includes a plurality of control circuits respectively provided to the plurality of programming portions, and each of the plurality of control circuits activates a corresponding spare memory line in response to the selecting signal of the prescribed level received from a corresponding logic circuit.
More preferably, the plurality of memory lines include n memory lines (the n is an integer not less than two), and the plurality of spare memory lines includes a first spare memory line and a second spare memory line. The plurality of programming portions include a first programming portion correspondingly provided to the first spare memory line, and a second programming portion correspondingly provided to the second spare memory line. The replacement programming portion further includes a first decode circuit for generating a signal for driving to an unselected state, based on a programmed state of the first programming portion, one of (nxe2x88x921) memory lines excluding a first memory line from the n memory lines, and a second decode circuit for generating a signal for driving to an unselected state, based on a programmed state of the second programming portion, one of (nxe2x88x921) memory lines excluding a second memory line different from the first memory line from the n memory lines. The select control circuit further includes a circuit for inactivating the first memory line using an output from the second decode circuit when the first memory line is defective and for inactivating the second memory line using an output from the first decode circuit when the second memory line is defective.
With the above-described semiconductor memory device, the repair can be performed using only the fuses of the number required for designating the memory lines (word lines or bit lines) to be replaced. As a result, the chip area can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.